A Modernistic Approach to Design Fault Tolerant Circuit Using LP-LFSR with Low Power Dissipation

The aim of testing of VLSI circuits is high-quality screening of the circuits by targeting performance related faults. A low hardware overhead test pattern generator (TPG) for scan based BIST that can detect the any faults in the circuit under test and analyze their response .It is a new fault coverage test pattern generator using a liner feedback shift register (LFSR) called FC-LFSR can perform the fault analysis and reduce the power of a circuit during test by generating three intermediate patterns between the random pattern s by using the less hardware. Modified scheme for the TPG by implemented LP-LFSR that provides test vectors which can reduce the switching activity during test operation primary input (PI) which can reduces the reduces the power consumption by utilizing less area and hardware resources .The experimental results for multiplier circuit being tested and analyzed response. Key wordsBIST, Test Pattern Generator (TPG), Liner Feedback Shift Register (LFSR), Low Power